dat a sheet product specification october 2001 discrete semiconductors buj105ab silicon diffused power transistor
nxp semiconductors product specification silicon diffused power transistor buj105ab general description high-voltage, high-speed planar-passivated npn power switching transistor in sot404 (d 2 -pak) surface-mount package intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching regulators, motor control systems, etc. quick reference data symbol parameter conditions typ. max. unit v cesm collector-emitter voltage peak value v be = 0 v - 700 v v cbo collector-base voltage (open emitter) - 700 v v ceo collector-emitter voltage (open base) - 400 v i c collector current (dc) - 8 a i cm collector current peak value - 16 a p tot total power dissipation t mb 25 ?c - 125 w v cesat collector-emitter saturation voltage i c = 4.0 a;i b = 0.8 a 0.3 1.0 v h fesat i c = 4.0 a; v ce = 5 v 11 15 t f fall time i c = 5 a; i b1 = 1 a 20 50 ns pinning - sot404 pin configuration symbol pin description 1 base 2 collector 3 emitter mb collector limiting values8 limiting values in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min. max. unit v cesm collector to emitter voltage v be = 0 v - 700 v v ceo collector to emitter voltage (open base) - 400 v v cbo collector to base voltage (open emitter) - 700 v i c collector current (dc) - 8 a i cm collector current peak value - 16 a i b base current (dc) - 4 a i bm base current peak value - 8 a p tot total power dissipation t mb 25 ?c - 125 w t stg storage temperature -65 150 ?c t j junction temperature - 150 ?c thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction to mounting - 1.0 k/w base r th j-a thermal resistance junction to ambient minimum footprint, fr4 board 55 - k/w 13 mb 2 b c e october 2001 1 rev 1.000
nxp semiconductors product specification silicon diffused power transistor buj105ab static characteristics t mb = 25 ?c unless otherwise specified symbol parameter conditions min. typ. max. unit i ces ,i cbo collector cut-off current 1 v be = 0 v; v ce = v cesmmax - - 0.2 ma i ces v be = 0 v; v ce = v cesmmax ; - - 0.5 ma t j = 125 ?c i ceo collector cut-off current v ceo = v ceommax (400v) - - 0.1 ma i ebo emitter cut-off current v eb = 9 v; i c = 0 a - - 1 ma v ceosust collector-emitter sustaining voltage i b = 0 a; i c = 10 ma; 400 - - v l = 25 mh v cesat collector-emitter saturation voltage i c = 4.0 a;i b = 0.8 a - 0.3 1.0 v v besat base-emitter saturation voltage i c = 4.0 a;i b = 0.8 a - 1.0 1.5 v h fe dc current gain i c = 1 ma; v ce = 5 v 10 14 34 h fe i c = 500 ma; v ce = 5 v 13 23 36 h fesat i c = 4.0 a; v ce = 5 v 8 11 15 dynamic characteristics t mb = 25 ?c unless otherwise specified symbol parameter conditions typ. max. unit switching times (resistive load) i con = 5 a; i bon = -i boff = 1 a; r l = 75 ohms; v bb2 = 4 v; t on turn-on time 0.65 1 s t s turn-off storage time 1.8 2.5 s t f turn-off fall time 0.3 0.5 s switching times (inductive load) i con = 5 a; i bon = 1 a; l b = 1 h; -v bb = 5 v t s turn-off storage time 1.2 1.7 s t f turn-off fall time 20 50 ns switching times (inductive load) i con = 5 a; i bon = 1 a; l b = 1 h; -v bb = 5 v; t j = 100 ?c t s turn-off storage time 1.4 1.9 s t f turn-off fall time 25 100 ns 1 measured with half sine-wave voltage (curve tracer). october 2001 2 rev 1.000
nxp semiconductors product specification silicon diffused power transistor buj105ab fig.1. test circuit for v ceosust . fig.2. oscilloscope display for v ceosust . fig.3. test circuit resistive load. v im = -6 to +8 v v cc = 250 v; t p = 20 s; = t p / t = 0.01. r b and r l calculated from i con and i bon requirements. fig. 4. switching times waveforms with resistive load. fig.5. test circuit inductive load. vcc = 300 v; -v be = 5 v; l c = 200 uh; l b = 1 uh fig.6. switching times waveforms with inductive load. + 50v 100-200r horizontal vertical oscilloscope 1r 6v 30-60 hz 300r ic ib 10 % 10 % 90 % 90 % ton toff ts tf ibon -iboff icon tr 30ns vce / v min vceosust ic / ma 10 100 250 0 lb ibon -vbb lc t.u.t. vcc tp t vcc r r t.u.t. 0 vim b l ic ib icon ibon -iboff t t ts tf toff 10 % 90 % october 2001 3 rev 1.000
nxp semiconductors product specification silicon diffused power transistor buj105ab fig.7. normalised power dissipation. pd% = 100pd/pd 25?c = f (t mb ) fig.8. typical dc current gain. h fe = f(i c ) parameter v ce fig.9. typical dc current gain. h fe = f(i c ) parameter v ce fig.10. collector-emitter saturation voltage. solid lines = typ values, v cesat = f(ib); t j =25?c. fig.11. base-emitter saturation voltage. solid lines = typ values, v besat = f(ic); at ic/ib =4. fig.12. collector-emitter saturation voltage. solid lines = typ values, v cesat = f(ic); at ic/ib =4. 0 20 40 60 80 100 120 140 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0.0 0.4 0.8 1.2 1.6 2.0 0.01 0.10 1.00 10.00 ib/a vcesat/v ic=1a 2a 3a 4a 0.01 0.05 0.1 0.3 1 2 3 5 10 2 5 10 15 20 30 50 ic/a hfe tj=100c 25c -40c vce=1v 0.1 0.5 1 2 5 10 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 ic/a vbesat/v tj=100c -40c 25c 0.01 0.05 0.1 0.3 1 2 3 5 10 2 5 10 15 20 30 50 ic/a hfe tj=100c 25c -40c vce=5v 0.2 0.4 0.6 1 2 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 ic/a vcesat/v tj=100c -40c 25c october 2001 4 rev 1.000
nxp semiconductors product specification silicon diffused power transistor buj105ab fig.13. transient thermal impedance. z th j-mb = f(t); parameter = t p /t fig.14. test circuit for reverse bias safe operating area. v clamp < 700v; v cc = 150v; -v be = 5v,3v & 1v; l b = 1h; l c = 200 h. fig.15. reverse bias safe operating area (t j < t jmax ) for -v be = 5v,3v & 1v. 10 z th(j-mb) (k/w) 1 10 -1 10 -2 = 0.5 0.2 0.1 single pulse 0.05 0.02 t p t p t p t t = 1 10 10 -1 10 -2 10 -3 10 -4 t p (s) 0 100 200 300 400 500 600 700 800 0 1 2 3 4 5 6 7 8 9 10 11 vceclamp/v ic/a -5v -3v -1v lb ibon -vbb lc t.u.t. vcc probe point vcl(rbsoar) october 2001 5 rev 1.000
nxp semiconductors product specification silicon diffused power transistor buj105ab mechanical data dimensions in mm net mass: 1.4 g fig.16. sot404 : centre pin connected to mounting base. mounting instructions dimensions in mm fig.17. sot404 : soldering pattern for surface mounting. notes 1. plastic meets ul94 v0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 october 2001 6 rev 1.000
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